Design specification: Help write block-level design specifications, run system-level simulations, and support chip-level architecture definition and documentation.
Implementation: Develop RTL in Verilog and take blocks through lint, clock domain crossing (CDC) analysis, synthesis, static timing analysis, timing closure, and top-level integration. Support DFT tasks.
Verification: Work with the verification team on test planning and execution, debug block- and system-level simulations, and support formal verification.
Flow and methodology: Help develop and improve the design flows and methods used across our interdisciplinary R&D group.
Validation and production: Work with the validation and production teams to create test plans and test vectors that ensure product quality and robustness.
Qualifications
Proactive, curious and eager to learn, great attention to details, positive, and great team work
Bachelor's or Master's Degree in Electrical or Computer Engineering
Digital FPGA/ASIC/IC design experience
Design-for-verification experience or understanding (assertion-based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
Self-starter and fast learner with excellent interpersonal skills
Track record of driving technical solutions across organizational boundaries and multiple technical disciplines
Preferred Qualifications
Significant experience with RTL coding in Verilog/SystemVerilog
Strong knowledge of Python scripting, Linux/Unix environment, and basic C/C++ programming
Strong knowledge of PCIe, Ethernet
Thorough understanding of ASIC design flow
Proficiency in Chinese would be considered an asset
Job Overview
Responsibilities
Design specification: Help write block-level design specifications, run system-level simulations, and support chip-level architecture definition and documentation.
Implementation: Develop RTL in Verilog and take blocks through lint, clock domain crossing (CDC) analysis, synthesis, static timing analysis, timing closure, and top-level integration. Support DFT tasks.
Verification: Work with the verification team on test planning and execution, debug block- and system-level simulations, and support formal verification.
Flow and methodology: Help develop and improve the design flows and methods used across our interdisciplinary R&D group.
Validation and production: Work with the validation and production teams to create test plans and test vectors that ensure product quality and robustness.
Qualifications
Proactive, curious and eager to learn, great attention to details, positive, and great team work
Bachelor's or Master's Degree in Electrical or Computer Engineering
5 years of relevant digital FPGA/ASIC/IC design experience
Significant experience with RTL coding in Verilog/SystemVerilog
Strong knowledge of Python scripting, Linux/Unix environment, and basic C/C++ programming
Strong knowledge of PCIe, Ethernet
Thorough understanding of ASIC design flow
Design-for-verification experience or understanding (assertion-based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
Self-starter and fast learner with excellent interpersonal skills
Track record of driving technical solutions across organizational boundaries and multiple technical disciplines
Proficiency in Chinese would be considered an asset
