Ethernet CTRL+PHY: Maximum 50/100Gbps
PCIe Gen5/CXL CTRL+PHY: Maximum 32Gbps per lane
DDR3/4/5 CTRL+PHY:6.4Gbps
MCR DDR5 CTRL+PHY:8.8~12.8Gbps
HBM3e/3/2e CTRL+PHY:9.6Gbps
INNOLINK/UCIe CTRL+PHY:Maximum 24Gbps
JESD 204B: Maximum 12.5Gbps per lane
JESD 204C: Maximum 32Gbps per lane
SDIO3.0: Support 1.8/3.3V, up to SDR104
Power consumption and Performance optimization
CPU Core Selection and Subsystem Design
Software full SDK delivery
Secure Boot and Secure Access Design
Product Board and whole Machine design
Systematic SI/PI simulation and Heat Dissipation design