INNOSILICON™ DDR5 IP includes the MRDIMM DDR5 PHY and DDR5/4 Combo PHY and corresponding controllers for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/RDIMM/LRDIMM/ UDIMM DDR5 devices. It is optimized for low-power and high-speed applications with robust timing and small silicon area. It supports all JEDEC DDR5/4 SDRAM components in the market. The PHY components contain DDR-specialized functional and utility high-performance I/Os, critical timing synchronization modules (TSM), and low-power/jitter DLLs with programmable fine-grain control for any SDRAM interface.