The INNOSILICON™ Delay-Locked Loop (DLL) PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock signals with precise timing. This IP ensures robust timing, minimizes skew, and operates efficiently with a small silicon footprint.
The DLL PHY is designed to generate precise phase-shifted clocks (e.g. 0°, 90°, 180°, 270°) based on a reference clock, enabling high-speed data capture and transmission. It consists of the Master DLL and Slave DLL, each serving specific roles in the clock distribution network.
