DDR3/4/5 CTRL+PHY:6.4Gbps
MCR DDR5 CTRL+PHY:8.8~12.8Gbps
GDDR6/7 CTRL+PHY:24/32Gbps
HBM3e/3/2e CTRL+PHY:9.6Gbps
INNOLINK/UCIe CTRL+PHY:Maximum 24Gbps
PCIe Gen5/CXL CTRL+PHY: Maximum 32Gbps per lane
Ethernet CTRL+PHY: Maximum 50Gbps
Self designed computing IP with customizable functionality and computing power (GPU\NPU, etc)
Design capability of NoC bus based on topology or mesh structure
Software friendly architecture design with best PPA
Various verification methods: Simulation | Formal | Emulation | FPGA
Rich experience in advanced process backend design with high density.
High coverage DFT design
Package and EVB design & SI/PI simulation.
Software SDK and Compiler delivery
Chip test program development
Mass production testing conduct