INNOSILICON™ PSRAM IP consists of a configurable PHY and RPC PHY and a controller. It provides the physical interface solutions for ICs requiring access to JEDEC compatible PSRAM/RPC devices. It is optimized for low-power and high-speed applications with robust timing and small silicon area. The PSRAM PHY supports AP memory UHS/OPI PSRAM components on the market, and the RPC PHY supports ETRON components on the market. The PHY components contain PSRAM-/RPC-specialized IO devices for utility and functionality, critical timing synchronization module (TSM), low-jitter PLL, the TX, and RX logic control for the interface.