The extremely computationally intensive device is powered by the tremendous computing power and massive bandwidth of the HPC Triad.

The extremely computationally intensive device is powered by the tremendous computing power and massive bandwidth of the HPC Triad.

Moore's law has been a fundamental principle for decades that states that the number of transistors on a chip will double every two years. However, as we enter the era of Big Data, new applications are driving the need for more performance and bandwidth. This is where Innosilicon comes in, as we offer our unique HPC Triad to help our clients leverage the semiconductor industry in order to design their own HPC systems for use in a variety of applications.

Multiple standards and protocols covered by Innosilicon's HPC Triad

One-stop IP, subsystem, and turnkey services for HPC solution

The world's breakthrough DDR technology improves the reliability and addresses the growing demand for faster performance and higher capacity, further breaking the "memory wall"

  • Innosilicon has led the way in breaking through 10Gbps, making it possible to mass-produce the world's fastest LPDDR5/5X/DDR5 IP, about twice the speed of the highest-end LPDDR5 (6.4Gbps) in the market.
  • The world's only HBM3.0/HBM2e COMBO IP ,clocked at up to 6.4Gbps/pin, supports up to 12 DRAM ICs per stack at 24GB capacity. With just one single stack of HBM3, the DRAM chip is capable of delivering 819GBps worth of memory bandwidth. The combo IP improves both power efficiency ,low energy per bit and offers flexibility of HBM type stacking depending on its availability and fluctuated price.
  • The fastest GDDR6/6X COMBO IP (PAM4-21Gbps), with a system bandwidth of more than 5Tb/s at 256-bit width, is driving the need for affordable ultra-bandwidth memory. GDDR6/6X is thought to be more economic than HBM and is a good replacement for some AI-centric markets.
  • The world's widest coverage and the industry's top DDR5 (DQ up to 8Gbps~5.6Gbps) and HBM3.0 (DQ up to 6.4Gbps) technologies are fully compliant with JEDEC standards, enabling computing vision, advanced autonomous driving, mobility edge and CPU/GPU/NPU HPC workloads.
  • Innosilicon’s DDR solution is a unique DDR platform in its ability to deliver cost-effective and highly flexible extended data block, which results in the highest levels of performance, features, power efficiency, and best area optimization for the desirable scenarios.

Chipset technology that breaks through the performance limit of a single chip. Innolink™ is the first developed IP solution where the physical layer is compatible with the UCIe standard.

  • Innolink™ is a highly integrated and modular SoC solution. It has been developed to be compatible with both UCIe specifications at the physical layer. A set of chiplets can be assembled in a mix and match LEGO which provides several advantages over a traditional system on chip (SoC), breaking through the limit of single-die manufacturing and the performance bottleneck of a single chip.
  • Innosilicon's cross-process and cross-package Chiplet interconnect solution has been successfully mass-produced on FinFet processes and has been attracted by many partners and customers.
  • Innolink™ provides a complete set of solutions for three interconnection methods, including Interposer, Substrate,, and PCB, covering D2D, C2C, B2B, P2P, and other possible connection scenarios, achieving the low latency, high power efficiency, and high density than the Serdes's solution.
  • Innosilicon also provides package design, reliability tests, silicon validation, signal integrity analysis, DFT insertion, thermal simulation, production test conversion, and other value-added services.

A comprehensive high-speed SerDes solutions to open up the express lane, , allowing a massive amount of data to be transmitted at blistering speeds.

  • The 32/56/64G SerDes is the current leader in performance and other key measures, having dominated a wide range of benchmarks, protocols and delivered a broad set of capabilities.
  • The multi-rate Serdes Support PCIe6/5/4, 2/3.0, SATA, XAUI, SATA, RapidIO, CXL2.0, JESD204 and other protocols. The new 112G SerDes is being developed, and will be available soon.
  • Innosilicon provides industry protocol compatible Serdes at an affordable price to customers for designing highly customized Retimer and Switch chips for enterprise servers market.
  • High performance and reliability SerDes products with the subsystem integrated and verified package are the key enablers for emerging technologies such as 5G communication, autonomous driving, artificial intelligence, data storage, cloud computing, high-resolution image processing, and the IoT.

Outperformance and Maturity

The design quality of the Triad, along with the fact that Triad is proven in multiple foundries on 10nm/8nm/7nm/5nm FinFet technology nodes, volume production by tier-one lead customers, and used in Innosilicon's Fantasy GPU family product line, makes it an excellent choice and high confidence for customers who are building high-performance computing ASICs.

Our IP Advantages

High cost performance and high reliability

A variety of comprehensive PHY & Controller solutions and Combo fitting various application scenarios, with high-reliability / high-performance / high-security / scalable design, fully supporting all mainstream FinFET processes.

High integration, low BOM cost

Worry-free integration, power and I/O optimization for small silicon area, PPA customization to perfectly meet customer’s application scenarios, fast one-stop integration with optimal area, power consumption and packaging.

Best practice, all-around optimization

One-stop PHY & Controller package and a full set of PCB and SI/PI, supporting full-custom hard macro and SI packaging solution including process/chip/package/PCB all-around optimization, within a short customization cycle of 2 to 3 months.

Customer-oriented service

Best-fit service for the customers, supporting various FPGA integration, SoC integration and specialized mass production, with a full custom solution of cross-design, cross-process and cross-package.

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