The Innosilicon eDP DP PHY is a highly reliable solution for your display interface requirements. It is fully compliant with DP 1.4 and eDP 1.4 standards, and capable of driving 2.7Gb/s per lane in configurations up to 4 lanes.

Designed with ease of integration in mind, it is configurable via its I2C, APB or CPU interface, and production testing is simplified through at-speed BIST, scan, loopback modes and boundary scan.

The PHY itself is fully self-contained, requiring no end user synthesis, and is optimized for both area and power. It contains all the necessary PHY components such as I/Os, primary and secondary ESD, PLL and the data symbol Synchronization/Serialization unit.

As with all Innosilicon IP, we are ready to provide the custom solution that meets your needs.


  • Silicon proven in GLOBALFOUNDRIES & SMIC
  • Easily ported into any technology
  • Uses standard chip digital and IO supplies
  • Compliant with DP 1.4 and eDP 1.4 standards
  • Drives up to 8.1 Gb/s per lane
  • Available in 1-4 lane PHY configurations
  • Output the link rate clock or half link rate clock, with or without SSC modulation
  • Supports transceiver for AUX channel working in 1MHz Manchester II coding mode
  • Area <0.53mm2 @12/14nm
  • Low pin count
  • 20-bit, 8b/10b data encoding, parallel input bus
  • Integrated low jitter, PLL
  • Embedded primary and secondary ESD provides  2000V HBM, 200V MM and 500V CDM
  • The design is latch-up tolerant to 200mA
  • Production test supported with BIST, scan, boundary scan and loop back
  • Deliverables support all major EDA tools
  • Optional DP 1.2 controller available




  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
    • Test chips and test boards
    • FPGA integration support
    • Chip level integration


  • Set top box
  • Video camera
  • A/V device
TELL US WHAT YOU NEED   We will provide a solution customized to best fit your needs.