Chiplet (INNOLINK™)

Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chips as if they were all on the same bus. Chiplets, defined as independent functional blocks making up a large chip, are pivotal in this new era of heterogeneous integration to achieve performance and efficiency gains. Based on this, Innosilicon launches the INNOLINK™ chiplet solution as a critical enabler of the power- and cost-efficient die-to-die (D2D), chip-to-chip (C2C), board-to-board (B2B) and package-to-package (P2P) connectivity for data center, networking, 5G, HPC and AI applications.

Innosilicon INNOLINK™ IP is designed to maximize bandwidth between dies / chips / boards / packages, compared to other interfaces available today, at lower power and smaller area budgets. By offering three interconnect options (A/B/C), INNOLINK™ IP can be tailored to customer’s different requirements with an easy-to-use system interface. It is architected for high programmability and flexibility, enabling optimized bandwidth up to over 1.5Tbps while maintaining signal integrity and low latency. Adopting the INNOLINK™ IP in your system will definitely benefit high performance computing ASICs/FPGAs, such as CPU, GPU, AI accelerator, and much more.





  • Meets the performance, efficiency and reliability  requirements of C2C/P2P interconnects
  • Already silicon proven
  • Delivers up to 24Gbps/pin
  • Single-ended DDR
  • Burst data
  • Forward clock
  • Low latency, Low power mode
  • Supports both Flip-chip and Silicon interposer
  • Software-defined IO direction and signal swap
  • Supports C4 Bump pitch of 100um~180um
  • Power efficiency of 0.7~1.1pJ/bit
  • Area efficiency of 0.4~1.0Tbps/mm2


  • Meets the performance, efficiency and reliability requirements of B2B/C2C interconnects
  • Already silicon proven
  • Delivers 56Gbps/pair with -36dB insertion loss
  • Leverages high-speed long reach SerDes
  • Differential signal
  • CDR based Rx
  • Optimized latency
  • Scalable to 4/8/16/32/64/128 lanes
  • PHY-independent training
  • Low power mode
  • Power efficiency of 1.8pJ/bit
  • Area efficiency 0.4Tbps/mm2


  • Meets the performance, efficiency and reliability requirements of D2D interconnects
  • Already silicon proven
  • Delivers 24Gbps/pin, per bit training
  • Single-ended DDR
  • Burst data, Low latency
  • App D2D, 2.5D/3D chiplet
  • Optimized for silicon interposer
  • Ultra low power, no CDR, no data package head
  • 0.4V IO voltage
  • Software-defined IO direction and signal swap
  • Supports bits redundant and lane repair
  • Micro Bump pitch of 40um~80um
  • Power efficiency of 0.45pJ/bit
  • Area efficiency up to 3.4Tbps/mm2


  • Available in any 40nm or below technology nodes
  • Significantly lower cost, shorter time to market, lower supply risks for OEMs and simpler architectural partitioning than the monolithic silicon integration
  • Offers leading performance, power, and area per terabit
  • Flexible configuration with support for silicon interposer, package substrate and PCB options
  • Customizable synthesis for any FPGAs and ASICs
  • Full support from IP delivery to production


  • High performance computing (HPC) applications
  • Next-generation data center
  • Networking
  • 5G communication
  • Artificial intelligence / machine learning (AI/ML) applications
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